iSine is pleased to announce the availability of the ExtremeECC™ IP (Intellectual Property) Block. The ExtremeECC™ IP block provides flexible implementation of Error Correcting Code to detect and correct up to 14 bits per code word, all in real time while streaming data.

ACCEL™ Silicon Available: ACCEL regulators and sensors are in production in 0.13µm and 80nm technologies. Demonstration units with embedded sensors are also available.

ACCEL™ Customer Design Wins: Customers have selected iSine's ACCEL to enhance product performance. ASIC designs are currently in progress with ACCEL implementations in 130nm and 80nm technologies.

iSine has joined the TSMC Design Center Alliance partnership: iSine is pleased to announce its engagement within the TSMC DCA program. With this program we can offer our customers the latest design libraries and lowest price quotes. We also work closely with the local TSMC sales staff on new and current customer programs. iSine is now one of the East Coast COT Design Centers for TSMC.

ASIC Design Center adds Magma tools: iSine has added the Magma Design Automation design tools to its extensive suite of design aids. With the Magma Design tools iSine further enhances its ability to meet critical time-to-market objectives, improve chip performance and handle even the most complex designs.

Low jitter PLL's have been completed in 0.18µm, 0.13µm and 45 nm technologies. Jitter specs of less than 6ps have been achieved.