Problem

Problem

A MEMS startup was behind schedule on design and layout for an analog-digital signal converter (ADC). 

Solution

Solution

An iSine engineer worked on site full time and weekends using Cadence Virtuoso Module Generator software. Layout, DRC and LVS were completed on time.

Results

Results

The customer's chip was taped out on time. The engineer worked with the customer two more times to help with more tapeouts.